Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
FIG. 1 illustrates an exemplary, generic memory array. A plurality of bitlines, labeled BL(a) through BL(f), may extend in parallel with one another, vertically through the array (or a portion thereof). A plurality of wordlines, labeled WL(a) through WL(f), may extend in parallel with one another, horizontally through the array (or a portion thereof). The wordlines may be at a higher level than (deposited above) the bitlines.
A plurality of memory cells, each labeled “mc”, are disposed in the array, and may be connected to selected ones of the wordlines and bitlines passing thereby. The memory cells illustrated in FIG. 1 are representative of many millions of memory cells that may be resident on a single chip. The memory cells may, generally, be any type of memory cell such as floating gate (FG) devices or charge-trapping devices such as nitride read only memory (NROM) devices, or other microelectronic cells or structures. The gates of field-effect transistor (FET) based memory cells, such as FG or NROM, may be connected to the wordlines, and source/drain diffusions of the FET-based memory cells may be connected between adjacent bitlines, as shown.
Flash Memory
Flash memory is a form of non-volatile memory (NVM) that can be electrically erased and reprogrammed. Flash memory architecture usually allows multiple memory locations to be erased or written in one programming operation. However, an erase operation is not mandatory for a Flash memory. A Flash memory can be designed to support only Program and Read operations. This kind of product is called OTP—“One Time Program”.
Generally, a Flash memory array may comprise a plurality (such as thousands) of Erase Sectors (ESecs, or ESs). The ESecs may be arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages, and Physical Sectors (PSecs, or PSs).
Refer, for example, to FIG. 4A, which illustrates an exemplary binary memory array having a plurality of Erase Sectors (ESecs), a plurality of Erase Sector Groups (ESGs), a plurality of Physical Pages, and a plurality of Physical Sectors (PSecs).
Generally, all of the Erase Sectors (ESecs) in a Flash memory array are the same as one another, and there are usually a binary number of ESecs in each Erase Sector Group (ESG), a binary number of Erase Sector Groups (ESGs) in a Physical Page, and a binary number of ESGs in a Physical Sector (PSec).
In Flash memory, when an erase command is applied, all of the pages in an ESec will be erased. The ESec is sometimes referred to as a “block”. In FIG. 4A, each of the little rectangular blocks represents an Erase Sector (ESec) and, as mentioned above, typically there are thousands (or more) of ESecs in a Flash memory array.
An Erase Sector Group (ESG) may comprise a number (such as 32) of wordlines, generally extending horizontally across the memory array. Or, another way of looking at it, an Erase Sector Group (ESG) may comprise a number of Erase Sectors (ESec) extending horizontally, next to one another, and sharing the same wordlines, across the memory array. See the dashed line box (and legend “one ESG”) in FIG. 4A.
Within a given Erase Sector (ESec), each wordline may be divided into a number (such as 4) of segments, which may be referred to as “pages”. A single wordline (WL) of a single given ESec may thus comprise several pages. Or, sometimes the term “page” may be used to refer to the aggregate of comparable (such as the first, second, third, eighth . . . ) segments from a few different wordlines in the ESec, rather than a segment of only one wordline in the ESec.
A number (such as tens of, such as 32) of Erase Sector Groups (ESGs) may be disposed one atop the other (sharing vertical bitlines), and may constitute a single Physical Sector (PSec). There may be a number (such as tens of, such as 32) of Physical Sectors (PSecs) disposed one atop the other. The total number of Erase Sector Groups (ESGs) would thus be the number of ESGs per PSec (such as 32) times the number of PSecs (such as 32). In this example, there would be 1024 ESGs.
As discussed in greater detail hereinbelow, the physical address of a given Erase Sector (ESec) may comprise three “pointers”,                one pointer (ysel) specifying which of the Erase Sectors (ESecs) within a given Erase Sector Group (ESG)        another pointer (esg) specifying which of the Erase Sector Groups (ESGs) within a given Physical Sector (PSec); and        another pointer (psec) specifying which of the Physical Sectors (PSecs) within the array.        
And, the physical address of a given memory location within the given Erase Sector (ESec) may comprise two pointers,                one pointer specifying the wordline within the given Erase Sector (ESec); and        another pointer specifying which page (portion of the wordline(s)) in the given Erase Sector (ESec).        
A Physical Sector (PSec) may comprise many more wordlines than an Erase Sector Group (ESG), since there are many ESGs in the PSec. A group of wordlines of a given PSec may be separated from another group of wordlines for another PSec by a select area comprising logic circuitry. When an address is asserted, only one given PSec may be active, and all others may be inactive.
Generally, the number of wordlines (WLs) in each of the Physical Sectors (PSecs) may be made to be the same as one another, to maintain the memory cells in the same physical “environment”. The number of wordlines (WLs) is typically a binary number, such as 1024 or 2048. This differs, for example, from technologies which may have different numbers of wordlines in different physical sectors of a given memory array. And, since the Physical Sectors (PSecs) are disposed one atop the other, they share the same bitlines (or sets of bitlines).
A Physical Page, also referred to as a “slice”, is generally a binary number (such as 32) of bitlines, and comprises vertically aligned segments of the Physical Sectors (PSecs), as well as corresponding vertically-aligned segments of the Erase Sector Groups (ESGs). Stated another way, a Physical Page (slice) comprises a column of many Erase Sectors (ESecs) which are disposed one above the other.
In a “binary array”, there are a binary number (such as 32) of PSecs, a binary number (such as 8) of Physical Pages (slices), and a binary number (such as 32) of ESecs. Usually, there are also a binary number (such as 32) of wordlines (WLs) in an ESec, and all of the ESecs in a Flash memory array are identical to one another.
Another grouping of Erase Sectors (ESecs), for example a number (typically binary, such as 32) of Erase Sectors (ESecs) disposed one above the other within a given Physical Sector (PSec) is not given a distinct name.
Memory Blocks and Non-Binary Array Architecture
A memory array may be arranged in blocks of memory, such as Erase Sectors (ESecs), erase sector groups (ESGs), physical pages (or slices) and Physical Sectors (PSecs). In a binary array, there are a number of each of these memory blocks, and the number for each memory block is a power of two (such as 8, 16 or 32). For example, a memory array may have 32 Erase Sectors (ESecs), 8 physical pages (slices) and 32 Physical Sectors (PSecs). Additionally, each Erase Sector (ESec) may comprise a number of wordlines which is also binary, such as 32.
Binary addressing schemes favor memories in which the number of addressable cells is a power of two. For a rectangular array of cells, this generally requires that the number of cell rows is a power of two, and that the number of cell columns is a power of two.
As applied to an array, “non-binary” refers to a rectangular array in which neither the number of columns nor the number of rows is a power of two. For example, 3×3 is a “non-binary” array, while 2×2 is a binary array
In a block architecture, such as a divided word architecture, the foregoing constraints can be applied to the arrangement of blocks.
Given a packaging standard, a non-binary array may provide a memory of greater capacity that is available using the nearest binary or semi-binary array.
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192, 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array (some of which have application to other types of NVM array), such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon) and the like used for NVM devices. Further description of NVM and related technologies may be found at “Non Volatile Memory Technology”, Vol. 1 & 2 (2005), Vol. 3 (2006) and Vol. 4 (2007), published by Saifun Semiconductor; “Microchip Fabrication”, by Peter Van Zant, 5th Edition 2004; “Application-Specific Integrated Circuits” by Michael John Sebastian Smith, 1997; “Semiconductor and Electronic Devices”, by Adir Bar-Lev, 2nd Edition, 1999; “Digital Integrated Circuits” by Jan. M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 2nd Edition, 2002 and materials presented at and through http://siliconnexus.com, “Design Considerations in Scaled SONOS Nonvolatile Memory Devices” found at: http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/presentations/bu_white_sonos_lehigh_univ.pdf, “SONOS Nonvolatile Semiconductor Memories for Space and Military Applications” found at: http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/papers/adams_d.pdf, “Philips Research—Technologies—Embedded Nonvolatile Memories” found at: http://www.research.philips.com/technologies/ics/nvmemories/index.html, and “Semiconductor Memory: Non-Volatile Memory (NVM)” found at: http://www.ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM.pdf, all of which are incorporated by reference herein in their entirety.
Glossary
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the disclosure most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning, unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks (®).
When glossary terms (such as abbreviations) are used in the description, no distinction should be made between the use of capital (uppercase) and lowercase letters. For example “ABC”, “abc” and “Abc”, or any other combination of upper and lower case letters with these 3 letters in the same order, should be considered to have the same meaning as one another, unless indicated or explicitly stated to be otherwise. The same commonality generally applies to glossary terms (such as abbreviations) which include subscripts, which may appear with or without subscripts, such as “Xyz” and “Xyz”. Additionally, plurals of glossary terms may or may not include an apostrophe before the final “s”—for example, ABCs or ABC's.    array memory cells may optionally be organized in an array of rows and columns, and may be connected to selected bit lines and word lines in the array. The array may be organized into various logical sections containing pluralities of memory cells, such as blocks, pages and physical sectors. Some of these sections may be physically isolated and operated independently from one another.    binary system The binary numeral system, or base-2 number system, is a numeral system that represents numeric values using only two symbols, usually “0” and “1”. Owing to its straightforward implementation in electronic circuitry, the binary system is used internally by virtually all modern computers. Many 1s and 0s can be strung together to represent larger numbers. Starting at the right is the “place” for “ones”, and there can be either 0 or 1 one's. The next “place” to the left is for “twos”, and there can be either 0 or 1 two's. The next “place” to the left is for “fours”, and there can be either 0 or 1 fours. The next “place” to the left is for “eights”, and there can be either 0 or 1 eights. This continues for as many places as desired, typically 4, 8, 16, 32 or 64 places.    bit The word “bit” is a shortening of the words “binary digit.” A bit refers to a digit in the binary numeral system (base 2). A given bit is either a binary “1” or “0”. For example, the number 1001011 is 7 bits long. The unit is sometimes abbreviated to “b”. Terms for large quantities of bits can be formed using the standard range of prefixes, such as kilobit (Kbit), megabit (Mbit) and gigabit (Gbit). A typical unit of 8 bits is called a Byte, and the basic unit for 128 Bytes to 16K Bytes is treated as a “page”. That is the “mathematical” definition of “bit”. In some cases, the actual (physical) left and right charge storage areas of an NROM cell are conveniently referred to as the left “bit” and the right “bit”, even though they may store more than one binary bit (with MLC, each storage area can store at least two binary bits). The intended meaning of “bit” (mathematical or physical) should be apparent from the context in which it is used.    BL short for bit line. The bit line is a conductor connected to the drain (or source) of a memory cell transistor.    ECC short for error correcting code. An error-correcting code (ECC) is a code in which each data signal conforms to specific rules of construction so that departures from this construction in the received signal can generally be automatically detected and corrected.    Flash memory Flash memory is a form of non-volatile memory (NVM) that can be electrically erased and reprogrammed. Flash memory architecture allows multiple memory locations to be erased or written in one programming operation. Two common types of flash memory are NOR and NAND flash. NOR and NAND flash get their names from the structure of the interconnections between memory cells. In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a NAND gate, and preventing cells from being read and programmed individually: the cells connected in series must be read in series.            Some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a random access storage area. NAND is best suited to flash devices requiring high capacity data storage. This type of flash architecture combines higher storage space with faster erase, write, and read capabilities over the execute in place advantage of the NOR architecture. See NAND, NOR.            mod short for modulo. In computing, the modulo operation finds the remainder of division of one number by another. You can think of doing modular arithmetic similar to the way you would, for example, figure time on a (12 hour) clock. In “modulo 12”, 10+3=1 because 10+3=13, of course, but 13 mod 12=1 because 13 divided by 12 leaves a remainder of 1.    NAND NAND flash architecture memories are accessed much like block devices such as hard disks or memory cards. The pages are typically 512 or 2,048 or 4,096 bytes in size. Associated with each page are usually a few bytes (typically 12-16 bytes) that are used for storage of an error detection (ED) and correction checksum. The pages are typically arranged in blocks, such as 32 pages of 512 bytes, 64 pages of 2,048 bytes, or 64 pages of 4,096 bytes. With NAND architecture, programming may be performed on a page basis, but erasure can only be performed on a block basis.            Most NAND devices are shipped from the factory with some bad blocks which are typically identified and marked according to a specified bad block marking strategy. The first physical block (block 0) is always guaranteed to be readable and free from errors. Hence, all vital pointers for partitioning and bad block management for the device are located inside this block (typically a pointer to the bad block tables). If the device is used for booting a system, this block may contain the master boot record.            NOR Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly without the need to copy them into RAM. NOR flash chips lack intrinsic bad block management, so when a flash block is worn out, the software or device driver controlling the device must handle this, or the device will cease to work reliably.    NROM short for nitride(d) read only memory. Generally, a FET-type device having a charge trapping medium such as a nitride layer for storing charges (electrons and holes) in two discrete areas, near the source and drain diffusions, respectively.    NVM short for non-volatile memory. NVM is computer memory that can retain the stored information even when not powered. Examples of non-volatile memory include read-only memory, flash memory, most types of magnetic computer storage devices (for example hard disks, floppy disk drives, and magnetic tape), optical disc drives, and early computer storage methods such as paper tape and punch cards. Non-volatile memory is typically used for the task of secondary storage, or long-term persistent storage. The most widely used form of primary storage today is a volatile form of random access memory (RAM), meaning that when the computer is shut down, anything contained in RAM is lost. Unfortunately most forms of non-volatile memory have limitations which make it unsuitable for use as primary storage. Typically non-volatile memory either costs more or performs worse than volatile random access memory. (By analogy, the simplest form of an NVM memory cell is a simple light switch. Indeed, such a switch can be set to one of two (binary) positions, and “memorize” that position.) NVM includes floating gate (FG) devices and NROM devices, as well a devices using optical, magnetic and phase change properties of materials.    page Generally, a grouping of memory cells can be termed a word, a grouping of words can be termed a page, and a grouping of pages can be termed a sector. Data may be accessed for reading and programming (or writing) by word or by page, while an entire sector is commonly accessed for erasing. Other definitions of “page” may be used throughout the industry and in this patent application.    RAM short for random access memory. RAM refers to data storage formats and equipment that allow the stored data to be accessed in any order—that is, at random, not just in sequence. In contrast, other types of memory devices (such as magnetic tapes, disks, and drums) can access data on the storage medium only in a predetermined order due to constraints in their mechanical design.    sector a part of the array, usually larger than a page, which usually contains a few pages. A minimum erase might include a sector. For example:            Erase Sector (ES, or ESec): Group of cells that are erased by single erase command        Physical Sector (PS, or PSec): Group of ES connected by single grid of Word Lines (WL) and Bit Lines (BL), sharing same set of drivers.            slice a portion of a memory array, such as a group of bitlines, that are connected to one sense amplifier (sense amp, “SA”)    virtual ground array a topological architecture of memory cells where there is an electrical connection between neighboring cells.    word line or wordline, (WL). A conductor normally connected to the gate of a memory cell transistor. The wordline may serve as the gate electrode of several of the memory cells.